Proposed resolution:

Change [atomics.types.operations] p18:

-18- Effects: Atomically, compares the value pointed to by object or by this for equality with that in expected, and if true, replaces the value pointed to by object or by this with desired, and if false, updates the value in expected with the value pointed to by object or by this. Further, if the comparison is true, memory is affected according to the value of success, and if the comparison is false, memory is affected according to the value of failure. When only one memory_order argument is supplied, the value of success is order, and the value of failure is order except that a value of memory_order_acq_rel shall be replaced by the value memory_order_acquire and a value of memory_order_release shall be replaced by the value memory_order_relaxed. If the comparison is true, Tthese operations are atomic read-modify-write operations (1.10). If the comparison is false, these operations are atomic load operations.

[ 2009-10 Santa Cruz: ]

NAD EditorialResolved. Addressed by N2992.

[ 2009-08-17 Handled by N2925. ]

[ 2009-07 post-Frankfurt: ]

This is likely to be addressed by Lawrence's upcoming paper. He will adopt the proposed resolution.

[ Batavia (2009-05): ]

We recommend the proposed resolution be reviewed by members of the Concurrency Subgroup.

[ Summit: ]

Group agrees with the resolution as proposed by Anthony Williams in the attached note.

[ Anthony Williams adds: ]

In [atomics.types.operations] p18 it says that "These operations are atomic read-modify-write operations" (final sentence). This is overly restrictive on the implementations of compare_exchange_weak and compare_exchange_strong on platforms without a native CAS instruction.

Addresses US 91 [CD1]

It is unclear whether or not a failed compare_exchange is a RMW operation (as used in [intro.multithread]).

Suggested solution:

Make failing compare_exchange operations not be RMW.